The present invention generally relates to semiconductor devices and fabrication process of semiconductor devices, and more particularly to a highly miniaturized high-speed semiconductor device and the fabrication process thereof.
With progress in the art of miniaturization process, it is now becoming possible, in the technology of ultra-fast semiconductor devices, to fabricate a semiconductor device having the gate length of 0.1 μm or less.
Generally, the operational speed of a semiconductor device increases with device miniaturization, while it is necessary with such highly miniaturized semiconductor devices to reduce the thickness of the gate insulation film with decrease of the gate length achieved by the device miniaturization in accordance with scaling law.
FIGS. 1A-1D show the process of forming a gate electrode according to a conventional process of fabricating semiconductor devices.
First, an insulation film 102 is formed on a substrate 101 of Si in a step shown in FIG. 1A, and a gate electrode 103 of polysilicon, or the like, is formed on the insulation film 102 in the step shown in FIG. 1B.
Next, in the step of FIG. 1C, the gate electrode film 103 is etched to form a gate electrode 103a, and a gate insulation film 102a is formed by patterning the insulation film 102 in the step shown in FIG. 1D.
For the gate insulation film 102a, a silicon oxide film (SiO2 film) has been used conventionally.
Now, when the gate length L0 is decreased to 0.1 μm or less, it becomes necessary to set the thickness TH0 of the gate insulation film to 1-2 nm or less in the case SiO2 is used for the gate insulation film, while there arises a problem of increase in the tunneling current with a gate insulation film of such an extremely small thickness, and it is not possible to avoid the problem of increase of gate leakage current with such a structure.
In view of these situations, there is a proposal of using a so-called high-K dielectric material, which has a specific dielectric constant much larger than that of an SiO2 film and thus has a small SiO2-equivalent film thickness in spite of the fact that the physical thickness of the film itself is large, for the gate insulation film. By using such high-K dielectrics, it becomes possible to suppress the gate leakage current caused by tunneling effect as a result of the use of the gate insulation film of the thickness of 2-5 nm also in the case the semiconductor device is a ultra-miniaturized semiconductor device having a gate length of 0.1 μm or less.
Patent Reference 1
SIA, EECA, EIAJ, KSIA and TSIA, “International Technology Road Map for Semiconductors” in 2001 update
However, such a high-K dielectric material has a nature entirely different form that of the conventionally used SiO2 film, and thus, it is not possible to apply a conventional etching process to the etching process of such a high-K dielectric material.
For example, there arises a difficulty in that etching rate becomes extremely small when such a conventional etching process is applied to a high-K dielectric film. Further, there arises a problem that it is difficult to secure sufficient etching selectivity with regard to the substrate, and it becomes difficult to control the etching process as desired.
Further, because of such poor controllability of etching, it was not possible to pattern the gate insulation properly, while this leads to the problem of degradation of performance of the semiconductor device.